If you are not up on Verilog, you can use the “Load Instance Code” button to decide a couple samples. You may test this if you want some thing actually simple:
module exam( enter a, output b ) assign b=~a endmodule
That makes a circuit like this:
The A button is are living, so clicking it will alter the minor fake LED to red alongside with the connected wires. It may not be clear, but you can drag parts about to fit you. You can also delete wires and build new connections. If there is a way to add and delete factors, we could not figure it out.
This isn’t a bad way to master Verilog given that you can immediately see what the code is performing. It is not flexible ample to be a workhorse simulator, however. For illustration, naming anything clk places a clock enter on the schematic, but using any other title as a clock leaves it as a button like “a” in the illustration earlier mentioned. There is no way to established the clock either.
This is fun, although. Yosys has a lot of capabilities we ordinarily do not use, such as the means to generate graphviz data files with schematics of the layout, though they are not as distinct as this. We’d adore to see this married with Falstad as the simulation motor so you could mainly use Verilog modules as portion of your simulation. That simulator can do digital circuits, it just doesn’t accept Verilog. If you want authentic simulation in your browser, attempt EDA Playground, which we use a ton.